<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=11"/>
<meta name="generator" content="Doxygen 1.14.0"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<title>DM-CtrlH7-BF-DevProgram: TIM Extended Timer input selection</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<script type="text/javascript" src="clipboard.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="navtreedata.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript" src="cookie.js"></script>
<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/searchdata.js"></script>
<script type="text/javascript" src="search/search.js"></script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr id="projectrow">
  <td id="projectlogo"><img alt="Logo" src="50x5.png"/></td>
  <td id="projectalign">
   <div id="projectname">DM-CtrlH7-BF-DevProgram<span id="projectnumber">&#160;beta 0.1</span>
   </div>
   <div id="projectbrief">C.ONE Studio Damiao Development Board Framework</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.14.0 -->
<script type="text/javascript">
var searchBox = new SearchBox("searchBox", "search/",'.html');
</script>
<script type="text/javascript">
$(function() { codefold.init(); });
</script>
<script type="text/javascript" src="menudata.js"></script>
<script type="text/javascript" src="menu.js"></script>
<script type="text/javascript">
$(function() {
  initMenu('',true,false,'search.php','Search',true);
  $(function() { init_search(); });
});
</script>
<div id="main-nav"></div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(function(){initNavTree('group___t_i_m_ex___timer___input___selection.html','',''); });
</script>
<div id="container">
<div id="doc-content">
<!-- window showing the filter options -->
<div id="MSearchSelectWindow"
     onmouseover="return searchBox.OnSearchSelectShow()"
     onmouseout="return searchBox.OnSearchSelectHide()"
     onkeydown="return searchBox.OnSearchSelectKey(event)">
</div>

<!-- iframe showing the search results (closed by default) -->
<div id="MSearchResultsWindow">
<div id="MSearchResults">
<div class="SRPage">
<div id="SRIndex">
<div id="SRResults"></div>
<div class="SRStatus" id="Loading">Loading...</div>
<div class="SRStatus" id="Searching">Searching...</div>
<div class="SRStatus" id="NoMatches">No Matches</div>
</div>
</div>
</div>
</div>

<div class="header">
  <div class="headertitle"><div class="title">TIM Extended Timer input selection <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m_ex.html">TIMEx</a> &raquo; <a class="el" href="group___t_i_m_ex___exported___constants.html">TIM Extended Exported Constants</a></div></div></div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga4d3d7a7e977f98110d2833d2feb7236a" id="r_ga4d3d7a7e977f98110d2833d2feb7236a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4d3d7a7e977f98110d2833d2feb7236a">TIM_TIM1_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gabba4a562a6e0f83acf57807e50de0de4" id="r_gabba4a562a6e0f83acf57807e50de0de4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabba4a562a6e0f83acf57807e50de0de4">TIM_TIM1_TI1_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga94308cf0e1eebb9a46fdd9c907b41cf5" id="r_ga94308cf0e1eebb9a46fdd9c907b41cf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga94308cf0e1eebb9a46fdd9c907b41cf5">TIM_TIM8_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga226e4035e59e5d1a566d7d673f858f35" id="r_ga226e4035e59e5d1a566d7d673f858f35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga226e4035e59e5d1a566d7d673f858f35">TIM_TIM8_TI1_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga11cd0b8d94b5ab46488aa3f2c3769d1f" id="r_ga11cd0b8d94b5ab46488aa3f2c3769d1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga11cd0b8d94b5ab46488aa3f2c3769d1f">TIM_TIM2_TI4_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga10665a31da680e9c23ff66b4e9f85b1e" id="r_ga10665a31da680e9c23ff66b4e9f85b1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga10665a31da680e9c23ff66b4e9f85b1e">TIM_TIM2_TI4_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a></td></tr>
<tr class="memitem:ga4d384c8a9c0687b64290b54c256a5152" id="r_ga4d384c8a9c0687b64290b54c256a5152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4d384c8a9c0687b64290b54c256a5152">TIM_TIM2_TI4_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a></td></tr>
<tr class="memitem:ga0449ea1c33b15b3f91222fcb3a239559" id="r_ga0449ea1c33b15b3f91222fcb3a239559"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0449ea1c33b15b3f91222fcb3a239559">TIM_TIM2_TI4_COMP1_COMP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td></tr>
<tr class="memitem:ga43e965c08be4bb981520165b1febf6c5" id="r_ga43e965c08be4bb981520165b1febf6c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga43e965c08be4bb981520165b1febf6c5">TIM_TIM3_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gad862ada9f9f69885f4f891cac338eb20" id="r_gad862ada9f9f69885f4f891cac338eb20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad862ada9f9f69885f4f891cac338eb20">TIM_TIM3_TI1_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga6d1cab356ab9db2d3a65327992bdf97f" id="r_ga6d1cab356ab9db2d3a65327992bdf97f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6d1cab356ab9db2d3a65327992bdf97f">TIM_TIM3_TI1_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:gaaf704734fd8855bfcfe8bf8591bd3d53" id="r_gaaf704734fd8855bfcfe8bf8591bd3d53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaaf704734fd8855bfcfe8bf8591bd3d53">TIM_TIM3_TI1_COMP1_COMP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td></tr>
<tr class="memitem:ga0887eba35836a73c891e2ad168a3da16" id="r_ga0887eba35836a73c891e2ad168a3da16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0887eba35836a73c891e2ad168a3da16">TIM_TIM5_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gabe5775cefd01431696ab62620b7a5d6b" id="r_gabe5775cefd01431696ab62620b7a5d6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabe5775cefd01431696ab62620b7a5d6b">TIM_TIM5_TI1_CAN_TMP</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga41a79c22055cb2f84a9ca574c3ab596c" id="r_ga41a79c22055cb2f84a9ca574c3ab596c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga41a79c22055cb2f84a9ca574c3ab596c">TIM_TIM5_TI1_CAN_RTP</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:ga56544cebe96b454970fd3f754d3c9c49" id="r_ga56544cebe96b454970fd3f754d3c9c49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga56544cebe96b454970fd3f754d3c9c49">TIM_TIM12_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gaf47b84ebb87bad97064fdb017ead9151" id="r_gaf47b84ebb87bad97064fdb017ead9151"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf47b84ebb87bad97064fdb017ead9151">TIM_TIM12_TI1_SPDIF_FS</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga203fd51591dbc76d09a12d1ca4e539a1" id="r_ga203fd51591dbc76d09a12d1ca4e539a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga203fd51591dbc76d09a12d1ca4e539a1">TIM_TIM15_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gad7f0c85a8acd135947bdb67db634e3b1" id="r_gad7f0c85a8acd135947bdb67db634e3b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad7f0c85a8acd135947bdb67db634e3b1">TIM_TIM15_TI1_TIM2_CH1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:gae48754f7fa79114b029d245eea699b84" id="r_gae48754f7fa79114b029d245eea699b84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae48754f7fa79114b029d245eea699b84">TIM_TIM15_TI1_TIM3_CH1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:gaf2c8be800c5ea6a82734ade8f5bb5e1e" id="r_gaf2c8be800c5ea6a82734ade8f5bb5e1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf2c8be800c5ea6a82734ade8f5bb5e1e">TIM_TIM15_TI1_TIM4_CH1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td></tr>
<tr class="memitem:ga53599dcd4f5502bf1c76670f03aac081" id="r_ga53599dcd4f5502bf1c76670f03aac081"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga53599dcd4f5502bf1c76670f03aac081">TIM_TIM15_TI1_RCC_LSE</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a>)</td></tr>
<tr class="memitem:ga4d4938b548affd930758e2801f48eb07" id="r_ga4d4938b548affd930758e2801f48eb07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4d4938b548affd930758e2801f48eb07">TIM_TIM15_TI1_RCC_CSI</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a>)</td></tr>
<tr class="memitem:ga2205065d06dc15721f52ccc6c7d6e0eb" id="r_ga2205065d06dc15721f52ccc6c7d6e0eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2205065d06dc15721f52ccc6c7d6e0eb">TIM_TIM15_TI1_RCC_MCO2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td></tr>
<tr class="memitem:gac24fe62f6e315b6bf3315b70e808ef81" id="r_gac24fe62f6e315b6bf3315b70e808ef81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac24fe62f6e315b6bf3315b70e808ef81">TIM_TIM15_TI2_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga3116230cad942525244192c4f0bb1fbe" id="r_ga3116230cad942525244192c4f0bb1fbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3116230cad942525244192c4f0bb1fbe">TIM_TIM15_TI2_TIM2_CH2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga18532138f0c7423e6acb642933937cbb">TIM_TISEL_TI2SEL_0</a>)</td></tr>
<tr class="memitem:gacc2c94f28892cfbc46fc27bab2d23cdd" id="r_gacc2c94f28892cfbc46fc27bab2d23cdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gacc2c94f28892cfbc46fc27bab2d23cdd">TIM_TIM15_TI2_TIM3_CH2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac432d94cbea0fec68e3cf56c8b25a532">TIM_TISEL_TI2SEL_1</a>)</td></tr>
<tr class="memitem:gadb9f1861b478966c9329ad9f540a4fcc" id="r_gadb9f1861b478966c9329ad9f540a4fcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gadb9f1861b478966c9329ad9f540a4fcc">TIM_TIM15_TI2_TIM4_CH2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga18532138f0c7423e6acb642933937cbb">TIM_TISEL_TI2SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac432d94cbea0fec68e3cf56c8b25a532">TIM_TISEL_TI2SEL_1</a>)</td></tr>
<tr class="memitem:gaf4435f9a5d0eb16d1b2b1192ad004392" id="r_gaf4435f9a5d0eb16d1b2b1192ad004392"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf4435f9a5d0eb16d1b2b1192ad004392">TIM_TIM16_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga0fbcfc41d3049d0f638e2024c3650a21" id="r_ga0fbcfc41d3049d0f638e2024c3650a21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0fbcfc41d3049d0f638e2024c3650a21">TIM_TIM16_TI1_RCC_LSI</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga921143f341cd81c4ce43f3d6ecae9df9" id="r_ga921143f341cd81c4ce43f3d6ecae9df9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga921143f341cd81c4ce43f3d6ecae9df9">TIM_TIM16_TI1_RCC_LSE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:ga9b830fb428d95bee93970c5405fb2fe3" id="r_ga9b830fb428d95bee93970c5405fb2fe3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9b830fb428d95bee93970c5405fb2fe3">TIM_TIM16_TI1_WKUP_IT</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td></tr>
<tr class="memitem:gab97c8da0527e5686a80a50f906225e02" id="r_gab97c8da0527e5686a80a50f906225e02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab97c8da0527e5686a80a50f906225e02">TIM_TIM17_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga3f1415fc8e6bf01ebdfad3c06f3bcc3c" id="r_ga3f1415fc8e6bf01ebdfad3c06f3bcc3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3f1415fc8e6bf01ebdfad3c06f3bcc3c">TIM_TIM17_TI1_SPDIF_FS</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga409efca3f95e233e2bf48908a7e25a94" id="r_ga409efca3f95e233e2bf48908a7e25a94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga409efca3f95e233e2bf48908a7e25a94">TIM_TIM17_TI1_RCC_HSE1MHZ</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:ga96722a6c22463858abfcafa371a6a835" id="r_ga96722a6c22463858abfcafa371a6a835"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga96722a6c22463858abfcafa371a6a835">TIM_TIM17_TI1_RCC_MCO1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td></tr>
<tr class="memitem:gaa2e648e7357bd2545a1eeacd922d0b05" id="r_gaa2e648e7357bd2545a1eeacd922d0b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa2e648e7357bd2545a1eeacd922d0b05">TIM_TIM23_TI4_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gaa706392ffbe746d070a46365453eff0e" id="r_gaa706392ffbe746d070a46365453eff0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa706392ffbe746d070a46365453eff0e">TIM_TIM23_TI4_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a></td></tr>
<tr class="memitem:ga19d293cc1ce67979391149b8b9ff7ecb" id="r_ga19d293cc1ce67979391149b8b9ff7ecb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga19d293cc1ce67979391149b8b9ff7ecb">TIM_TIM23_TI4_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a></td></tr>
<tr class="memitem:gae33fc9dfbd92dfa798438e41cbe461c7" id="r_gae33fc9dfbd92dfa798438e41cbe461c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae33fc9dfbd92dfa798438e41cbe461c7">TIM_TIM23_TI4_COMP1_COMP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td></tr>
<tr class="memitem:ga172efd80a7592e1b949d12e7439c0b6a" id="r_ga172efd80a7592e1b949d12e7439c0b6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga172efd80a7592e1b949d12e7439c0b6a">TIM_TIM24_TI1_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gafcabd2f57f3e9de1ef4863154ecfe810" id="r_gafcabd2f57f3e9de1ef4863154ecfe810"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafcabd2f57f3e9de1ef4863154ecfe810">TIM_TIM24_TI1_CAN_TMP</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td></tr>
<tr class="memitem:ga668d33771d5bb3601f5981c7d5f7affe" id="r_ga668d33771d5bb3601f5981c7d5f7affe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga668d33771d5bb3601f5981c7d5f7affe">TIM_TIM24_TI1_CAN_RTP</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td></tr>
<tr class="memitem:gaf6550208fd6a5aafc1ed97b65a836dc4" id="r_gaf6550208fd6a5aafc1ed97b65a836dc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf6550208fd6a5aafc1ed97b65a836dc4">TIM_TIM24_TI1_CAN_SOC</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="ga56544cebe96b454970fd3f754d3c9c49" name="ga56544cebe96b454970fd3f754d3c9c49"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga56544cebe96b454970fd3f754d3c9c49">&#9670;&#160;</a></span>TIM_TIM12_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM12_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM12 TI1 is connected to GPIO </p>

</div>
</div>
<a id="gaf47b84ebb87bad97064fdb017ead9151" name="gaf47b84ebb87bad97064fdb017ead9151"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf47b84ebb87bad97064fdb017ead9151">&#9670;&#160;</a></span>TIM_TIM12_TI1_SPDIF_FS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM12_TI1_SPDIF_FS&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM12 TI1 is connected to SPDIF FS </p>

</div>
</div>
<a id="ga203fd51591dbc76d09a12d1ca4e539a1" name="ga203fd51591dbc76d09a12d1ca4e539a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga203fd51591dbc76d09a12d1ca4e539a1">&#9670;&#160;</a></span>TIM_TIM15_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga4d4938b548affd930758e2801f48eb07" name="ga4d4938b548affd930758e2801f48eb07"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4d4938b548affd930758e2801f48eb07">&#9670;&#160;</a></span>TIM_TIM15_TI1_RCC_CSI</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_RCC_CSI&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to RCC CSI </p>

</div>
</div>
<a id="ga53599dcd4f5502bf1c76670f03aac081" name="ga53599dcd4f5502bf1c76670f03aac081"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga53599dcd4f5502bf1c76670f03aac081">&#9670;&#160;</a></span>TIM_TIM15_TI1_RCC_LSE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_RCC_LSE&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to RCC LSE </p>

</div>
</div>
<a id="ga2205065d06dc15721f52ccc6c7d6e0eb" name="ga2205065d06dc15721f52ccc6c7d6e0eb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2205065d06dc15721f52ccc6c7d6e0eb">&#9670;&#160;</a></span>TIM_TIM15_TI1_RCC_MCO2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_RCC_MCO2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcab70466ce0c2bf5b052ef9963d0c7">TIM_TISEL_TI1SEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to RCC MCO2 </p>

</div>
</div>
<a id="gad7f0c85a8acd135947bdb67db634e3b1" name="gad7f0c85a8acd135947bdb67db634e3b1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad7f0c85a8acd135947bdb67db634e3b1">&#9670;&#160;</a></span>TIM_TIM15_TI1_TIM2_CH1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_TIM2_CH1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to TIM2 CH1 </p>

</div>
</div>
<a id="gae48754f7fa79114b029d245eea699b84" name="gae48754f7fa79114b029d245eea699b84"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae48754f7fa79114b029d245eea699b84">&#9670;&#160;</a></span>TIM_TIM15_TI1_TIM3_CH1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_TIM3_CH1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to TIM3 CH1 </p>

</div>
</div>
<a id="gaf2c8be800c5ea6a82734ade8f5bb5e1e" name="gaf2c8be800c5ea6a82734ade8f5bb5e1e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf2c8be800c5ea6a82734ade8f5bb5e1e">&#9670;&#160;</a></span>TIM_TIM15_TI1_TIM4_CH1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI1_TIM4_CH1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI1 is connected to TIM4 CH1 </p>

</div>
</div>
<a id="gac24fe62f6e315b6bf3315b70e808ef81" name="gac24fe62f6e315b6bf3315b70e808ef81"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac24fe62f6e315b6bf3315b70e808ef81">&#9670;&#160;</a></span>TIM_TIM15_TI2_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI2_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI2 is connected to GPIO </p>

</div>
</div>
<a id="ga3116230cad942525244192c4f0bb1fbe" name="ga3116230cad942525244192c4f0bb1fbe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3116230cad942525244192c4f0bb1fbe">&#9670;&#160;</a></span>TIM_TIM15_TI2_TIM2_CH2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI2_TIM2_CH2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga18532138f0c7423e6acb642933937cbb">TIM_TISEL_TI2SEL_0</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI2 is connected to TIM2 CH2 </p>

</div>
</div>
<a id="gacc2c94f28892cfbc46fc27bab2d23cdd" name="gacc2c94f28892cfbc46fc27bab2d23cdd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacc2c94f28892cfbc46fc27bab2d23cdd">&#9670;&#160;</a></span>TIM_TIM15_TI2_TIM3_CH2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI2_TIM3_CH2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac432d94cbea0fec68e3cf56c8b25a532">TIM_TISEL_TI2SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI2 is connected to TIM3 CH2 </p>

</div>
</div>
<a id="gadb9f1861b478966c9329ad9f540a4fcc" name="gadb9f1861b478966c9329ad9f540a4fcc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadb9f1861b478966c9329ad9f540a4fcc">&#9670;&#160;</a></span>TIM_TIM15_TI2_TIM4_CH2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM15_TI2_TIM4_CH2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga18532138f0c7423e6acb642933937cbb">TIM_TISEL_TI2SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac432d94cbea0fec68e3cf56c8b25a532">TIM_TISEL_TI2SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM15_TI2 is connected to TIM4 CH2 </p>

</div>
</div>
<a id="gaf4435f9a5d0eb16d1b2b1192ad004392" name="gaf4435f9a5d0eb16d1b2b1192ad004392"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf4435f9a5d0eb16d1b2b1192ad004392">&#9670;&#160;</a></span>TIM_TIM16_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM16_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM16 TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga921143f341cd81c4ce43f3d6ecae9df9" name="ga921143f341cd81c4ce43f3d6ecae9df9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga921143f341cd81c4ce43f3d6ecae9df9">&#9670;&#160;</a></span>TIM_TIM16_TI1_RCC_LSE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM16_TI1_RCC_LSE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM16 TI1 is connected to RCC LSE </p>

</div>
</div>
<a id="ga0fbcfc41d3049d0f638e2024c3650a21" name="ga0fbcfc41d3049d0f638e2024c3650a21"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0fbcfc41d3049d0f638e2024c3650a21">&#9670;&#160;</a></span>TIM_TIM16_TI1_RCC_LSI</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM16_TI1_RCC_LSI&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM16 TI1 is connected to RCC LSI </p>

</div>
</div>
<a id="ga9b830fb428d95bee93970c5405fb2fe3" name="ga9b830fb428d95bee93970c5405fb2fe3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9b830fb428d95bee93970c5405fb2fe3">&#9670;&#160;</a></span>TIM_TIM16_TI1_WKUP_IT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM16_TI1_WKUP_IT&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM16 TI1 is connected to WKUP_IT </p>

</div>
</div>
<a id="gab97c8da0527e5686a80a50f906225e02" name="gab97c8da0527e5686a80a50f906225e02"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab97c8da0527e5686a80a50f906225e02">&#9670;&#160;</a></span>TIM_TIM17_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM17_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM17 TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga409efca3f95e233e2bf48908a7e25a94" name="ga409efca3f95e233e2bf48908a7e25a94"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga409efca3f95e233e2bf48908a7e25a94">&#9670;&#160;</a></span>TIM_TIM17_TI1_RCC_HSE1MHZ</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM17_TI1_RCC_HSE1MHZ&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM17 TI1 is connected to RCC HSE 1Mhz </p>

</div>
</div>
<a id="ga96722a6c22463858abfcafa371a6a835" name="ga96722a6c22463858abfcafa371a6a835"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga96722a6c22463858abfcafa371a6a835">&#9670;&#160;</a></span>TIM_TIM17_TI1_RCC_MCO1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM17_TI1_RCC_MCO1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM17 TI1 is connected to RCC MCO1 </p>

</div>
</div>
<a id="ga3f1415fc8e6bf01ebdfad3c06f3bcc3c" name="ga3f1415fc8e6bf01ebdfad3c06f3bcc3c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3f1415fc8e6bf01ebdfad3c06f3bcc3c">&#9670;&#160;</a></span>TIM_TIM17_TI1_SPDIF_FS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM17_TI1_SPDIF_FS&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM17 TI1 is connected to SPDIF FS </p>

</div>
</div>
<a id="gabba4a562a6e0f83acf57807e50de0de4" name="gabba4a562a6e0f83acf57807e50de0de4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabba4a562a6e0f83acf57807e50de0de4">&#9670;&#160;</a></span>TIM_TIM1_TI1_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_TI1_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM1_TI1 is connected to COMP1 OUT </p>

</div>
</div>
<a id="ga4d3d7a7e977f98110d2833d2feb7236a" name="ga4d3d7a7e977f98110d2833d2feb7236a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4d3d7a7e977f98110d2833d2feb7236a">&#9670;&#160;</a></span>TIM_TIM1_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM1_TI1 is connected to GPIO </p>

</div>
</div>
<a id="gaa706392ffbe746d070a46365453eff0e" name="gaa706392ffbe746d070a46365453eff0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa706392ffbe746d070a46365453eff0e">&#9670;&#160;</a></span>TIM_TIM23_TI4_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_TI4_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM23_TI4 is connected to COMP1 OUT </p>

</div>
</div>
<a id="gae33fc9dfbd92dfa798438e41cbe461c7" name="gae33fc9dfbd92dfa798438e41cbe461c7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae33fc9dfbd92dfa798438e41cbe461c7">&#9670;&#160;</a></span>TIM_TIM23_TI4_COMP1_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_TI4_COMP1_COMP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT </p>

</div>
</div>
<a id="ga19d293cc1ce67979391149b8b9ff7ecb" name="ga19d293cc1ce67979391149b8b9ff7ecb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga19d293cc1ce67979391149b8b9ff7ecb">&#9670;&#160;</a></span>TIM_TIM23_TI4_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_TI4_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM23_TI4 is connected to COMP2 OUT </p>

</div>
</div>
<a id="gaa2e648e7357bd2545a1eeacd922d0b05" name="gaa2e648e7357bd2545a1eeacd922d0b05"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa2e648e7357bd2545a1eeacd922d0b05">&#9670;&#160;</a></span>TIM_TIM23_TI4_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_TI4_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM23_TI4 is connected to GPIO </p>

</div>
</div>
<a id="ga668d33771d5bb3601f5981c7d5f7affe" name="ga668d33771d5bb3601f5981c7d5f7affe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga668d33771d5bb3601f5981c7d5f7affe">&#9670;&#160;</a></span>TIM_TIM24_TI1_CAN_RTP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_TI1_CAN_RTP&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM24_TI1 is connected to CAN RTP </p>

</div>
</div>
<a id="gaf6550208fd6a5aafc1ed97b65a836dc4" name="gaf6550208fd6a5aafc1ed97b65a836dc4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf6550208fd6a5aafc1ed97b65a836dc4">&#9670;&#160;</a></span>TIM_TIM24_TI1_CAN_SOC</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_TI1_CAN_SOC&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM24_TI1 is connected to CAN SOC </p>

</div>
</div>
<a id="gafcabd2f57f3e9de1ef4863154ecfe810" name="gafcabd2f57f3e9de1ef4863154ecfe810"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafcabd2f57f3e9de1ef4863154ecfe810">&#9670;&#160;</a></span>TIM_TIM24_TI1_CAN_TMP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_TI1_CAN_TMP&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM24_TI1 is connected to CAN TMP </p>

</div>
</div>
<a id="ga172efd80a7592e1b949d12e7439c0b6a" name="ga172efd80a7592e1b949d12e7439c0b6a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga172efd80a7592e1b949d12e7439c0b6a">&#9670;&#160;</a></span>TIM_TIM24_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM24_TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga10665a31da680e9c23ff66b4e9f85b1e" name="ga10665a31da680e9c23ff66b4e9f85b1e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga10665a31da680e9c23ff66b4e9f85b1e">&#9670;&#160;</a></span>TIM_TIM2_TI4_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_TI4_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM2_TI4 is connected to COMP1 OUT </p>

</div>
</div>
<a id="ga0449ea1c33b15b3f91222fcb3a239559" name="ga0449ea1c33b15b3f91222fcb3a239559"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0449ea1c33b15b3f91222fcb3a239559">&#9670;&#160;</a></span>TIM_TIM2_TI4_COMP1_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_TI4_COMP1_COMP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0b9c7718f9609776afdbb0ebcc3832">TIM_TISEL_TI4SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT </p>

</div>
</div>
<a id="ga4d384c8a9c0687b64290b54c256a5152" name="ga4d384c8a9c0687b64290b54c256a5152"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4d384c8a9c0687b64290b54c256a5152">&#9670;&#160;</a></span>TIM_TIM2_TI4_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_TI4_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf6106b6c27078a60113e888b0142ccb8">TIM_TISEL_TI4SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM2_TI4 is connected to COMP2 OUT </p>

</div>
</div>
<a id="ga11cd0b8d94b5ab46488aa3f2c3769d1f" name="ga11cd0b8d94b5ab46488aa3f2c3769d1f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga11cd0b8d94b5ab46488aa3f2c3769d1f">&#9670;&#160;</a></span>TIM_TIM2_TI4_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_TI4_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM2_TI4 is connected to GPIO </p>

</div>
</div>
<a id="gad862ada9f9f69885f4f891cac338eb20" name="gad862ada9f9f69885f4f891cac338eb20"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad862ada9f9f69885f4f891cac338eb20">&#9670;&#160;</a></span>TIM_TIM3_TI1_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM3_TI1_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM3_TI1 is connected to COMP1 OUT </p>

</div>
</div>
<a id="gaaf704734fd8855bfcfe8bf8591bd3d53" name="gaaf704734fd8855bfcfe8bf8591bd3d53"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaf704734fd8855bfcfe8bf8591bd3d53">&#9670;&#160;</a></span>TIM_TIM3_TI1_COMP1_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM3_TI1_COMP1_COMP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT </p>

</div>
</div>
<a id="ga6d1cab356ab9db2d3a65327992bdf97f" name="ga6d1cab356ab9db2d3a65327992bdf97f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6d1cab356ab9db2d3a65327992bdf97f">&#9670;&#160;</a></span>TIM_TIM3_TI1_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM3_TI1_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM3_TI1 is connected to COMP2 OUT </p>

</div>
</div>
<a id="ga43e965c08be4bb981520165b1febf6c5" name="ga43e965c08be4bb981520165b1febf6c5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga43e965c08be4bb981520165b1febf6c5">&#9670;&#160;</a></span>TIM_TIM3_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM3_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM3_TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga41a79c22055cb2f84a9ca574c3ab596c" name="ga41a79c22055cb2f84a9ca574c3ab596c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga41a79c22055cb2f84a9ca574c3ab596c">&#9670;&#160;</a></span>TIM_TIM5_TI1_CAN_RTP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM5_TI1_CAN_RTP&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad452efbdd8b96c975f09b1c10eb43c90">TIM_TISEL_TI1SEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM5_TI1 is connected to CAN RTP </p>

</div>
</div>
<a id="gabe5775cefd01431696ab62620b7a5d6b" name="gabe5775cefd01431696ab62620b7a5d6b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabe5775cefd01431696ab62620b7a5d6b">&#9670;&#160;</a></span>TIM_TIM5_TI1_CAN_TMP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM5_TI1_CAN_TMP&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM5_TI1 is connected to CAN TMP </p>

</div>
</div>
<a id="ga0887eba35836a73c891e2ad168a3da16" name="ga0887eba35836a73c891e2ad168a3da16"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0887eba35836a73c891e2ad168a3da16">&#9670;&#160;</a></span>TIM_TIM5_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM5_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM5_TI1 is connected to GPIO </p>

</div>
</div>
<a id="ga226e4035e59e5d1a566d7d673f858f35" name="ga226e4035e59e5d1a566d7d673f858f35"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga226e4035e59e5d1a566d7d673f858f35">&#9670;&#160;</a></span>TIM_TIM8_TI1_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_TI1_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac8352e91e70524bf299ae524b17fc4b2">TIM_TISEL_TI1SEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM8_TI1 is connected to COMP2 OUT </p>

</div>
</div>
<a id="ga94308cf0e1eebb9a46fdd9c907b41cf5" name="ga94308cf0e1eebb9a46fdd9c907b41cf5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga94308cf0e1eebb9a46fdd9c907b41cf5">&#9670;&#160;</a></span>TIM_TIM8_TI1_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_TI1_GPIO&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM8_TI1 is connected to GPIO </p>

</div>
</div>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="page-nav" class="page-nav-panel">
<div id="page-nav-resize-handle"></div>
<div id="page-nav-tree">
<div id="page-nav-contents">
</div><!-- page-nav-contents -->
</div><!-- page-nav-tree -->
</div><!-- page-nav -->
</div><!-- container -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
  <ul>
    <li class="footer">Generated by <a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.14.0 </li>
  </ul>
</div>
</body>
</html>
